Please, cite the relevant papers in this page if you refer to them in your work. You can link to any of the papers here from your web site.

Journals

  1. Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman Unsal, Adrian Cristal, Ibrahim Hur, Mateo Valero, Profiling and Optimizing Transactional Memory Applications, IJPP'11: International Journal of Parallel Programming, July 2011. [BibTeX]

Conferences

  1. Srdjan Stipic, Saša Tomić, Ferad Zyulkyarov, Adrián Cristal, Osman Unsal, Mateo Valero, TagTM - Accelerating STMs with hardware tags for fast meta-data access, DATE'12: Proc. 2012 Design, Automation & Test in Europe, March 2012.[BibTeX, ppt, pptx]
  2. Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman Unsal, Adrian Cristal, Ibrahim Hur, Mateo Valero, Discovering and Understanding Performance Bottlenecks in Transactional Applications, PACT'10: Proc. 19th International Conference on Parallel Architectures and Compilation Techniques, September 2010. ( Best Paper)
    [BibTeX, ppt, pptx]
  3. Ferad Zyulkyarov, Tim Harris, Osman Unsal, Adrian Cristal, Mateo Valero, Debugging Programs that use Atomic Blocks and Transactional Memory, PPoPP'10: Proc. 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, January 2010.
    [BibTeX, ppt, pptx]
  4. Vladimir Gajinov, Ferad Zyulkyarov, Osman Unsal, Adrian Cristal, Eduard Ayguade, Tim Harris, Mateo Valero, QuakeTM: Parallelizing a Complex Serial Application Using Transactional Memory , ICS'09: Proc. 23rd ACM SIGARCH International Conference on Supercomputing, June 2009
    [BibTeX, ppt, pptx]
  5. Ferad Zyulkyarov, Vladimir Gajinov, Osman Unsal, Adrian Cristal, Eduard Ayguade, Tim Harris, Mateo Valero, Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server , PPoPP'09: Proc. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Feb. 2009
    [BibTeX, ppt, pptx]
  6. Byurhan Hyusein, Ahmed Patel, Ferad Zyulkyarov, Comparison of New Simple Weighting Functions for Web Documents against Existing Methods, ISCIS'03: Proc. 18th International Symposium on Computer and Information Sciences, November 2003
    [BibTeX, The original publication is available at www.springerlink.com.]

Workshops

  1. Ferad Zyulkyarov, Sanja Cvijic,Osman Unsal, Adrian Cristal, Eduard Ayguade, Tim Harris, Mateo Valero, WormBench - A Configurable Workload for Evaluating Transactional Memory Systems, MEDEA '08: Workshop on MEmory performance: DEaling with Applications, systems and architecture, October 2008.
    BibTeX
  2. Ferad Zyulkyarov, Milos Milovanovic, Osman Unsal, Adrian Cristal, Eduard Ayguade, Tim Harris, Mateo Valero, Memory Management for Transaction Processing Core in Heterogeneous Chip-Multiprocessors, OSHMA '07: Workshop on Operating System support for Heterogeneous Multicore Architectures, September 2007
    BibTeX
  3. Ferad Zyulkyarov, Osman Unsal, Adrian Cristal, Mateo Valero, Synthetic Workloads for Transactional Memory. ACACES 2007, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. Laquila, July 18th. Academia Press, ISBN 978 90 382 1127 5, pp. 135-137, 2007
  4. Milos Milovanovic, Osman Unsal, Adrian Cristal, Ferad Zyulkyarov, Mateo Valero, Compiler Support for Using Transactional Memory in C/C++ Applications, INTERACT-11: Workshop on Interaction between Compilers and Computer Architecture, February 2007
    BibTeX

Technical Reports

  1. PhD Thesis Poroposal - Programming, Debugging, Profiling and Optimizing Transactional Memory Applications, Universitat Politecnica de Catalunya, Departament d'Arquitectura de Computadors, 01.07.2010.
    [doc, docx]
  2. Ferad Zyulkyarov, Sanja Cvijic, Osman Unsal, Adrian Cristal,Eduard Ayguade, Tim Harris, Mateo Valero, WormBench - Technical Report, Universitat Politecnica de Catalunya, Departament d'Arquitectura de Computadors, Technical Report UPC-DAC-RR-CAP-2008-23, August 2008.
  3. Ferad Zyulkyarov, Milos Milovanovic, Osman Unsal, Adrian Cristal, Eduard Ayguade, Mateo Valero, Tim Harris , Transaction Processing Core for Accelerating Software Transactional Memory, Universitat Politecnica de Catalunya, Departament d'Arquitectura de Computadors, Technical Report UPC-DAC-RR-GEN-2007-5, August 2007.

Presentations and Talks

PhD Thesis

Programming, Debugging, Profiling and Optimizing Transactional Memory Programs